教員情報 - 吉村　正義 | 京都産業大学

ヨシムラ　マサヨシ YOSHIMURA MASAYOSHI
吉村　正義

所属

京都産業大学情報理工学部情報理工学科

職種教授

著書・論文歴
2026/03	論文	A Multiple Target Seed Generation Method for Random Pattern Resistant Faults on Built-In Self-Test IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E109A (3),604-613頁
2025	論文	PBO-Based Pattern Replacement for Compacting Diagnostic Patterns to Achieve Complete Diagnostic Resolution. DFT,1-6頁
2024/03	論文	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E107A (3),583-591頁
2024	論文	A Low Power Oriented Multiple Target Test Generation Method for 2-Cycle Gate-Exhaustive Faults 2024 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS, DFT,1-6頁
2023	論文	A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT),1-6頁
2023	論文	An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT),1-6頁
2023	論文	An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT),1-6頁
2022	論文	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level 2022 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS, DFT,1-6頁
2020	論文	A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method 2020 26TH IEEE INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2020),1-4頁
2020	論文	A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT 2020 33RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT),1-6頁
2019	論文	A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths 2019 IEEE 25TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2019),293-298頁
2019	論文	A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively 2019 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT),1-6頁
2019	論文	A State Assignment Method to Improve Transition Fault Coverage for Controllers 2019 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT),1-4頁
2019	論文	An efficient SAT-attack algorithm against logic encryption 2019 IEEE 25TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2019),44-47頁
2018	論文	A Capture Safe Static Test Compaction Method Based on Don't Cares 2018 IEEE 24TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2018),195-200頁
2018	論文	A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification 2018 IEEE 24TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2018),43-46頁
2018	論文	A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns 2018 IEEE 24TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2018),228-231頁
2017/12	論文	A Don ’t Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT IEICE Transactions on Fundamentals E100-A (12) (共著)
2017/12	論文	A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A (12),2824-2833頁
2017	論文	A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations 2017 IEEE 22ND PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING (PRDC 2017),221-222頁
2017	論文	Controller Augmentation and Test Point Insertion at RTL for Concurrent Operational Unit Testing 2017 IEEE 23RD INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS),17-20頁
2015/02/13	論文	スキャンベース攻撃を考慮した暗号LSIのテスト手法—Test Method for Encryption LSI against Scan-based Attacks 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 (446),25-30頁
2015	論文	A Don't Care Filling Method to Reduce Capture Power based on Correlation of FF Transitions 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS),13-18頁
2013/09	論文	A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E96D (9),1994-2002頁
2013/09	論文	A Test Compaction Oriented Don’t Care Identification Method Based on X-bit Distribution IEICE Transaction on Information and Systems E96-D (9),1994-2002頁 (共著)
2013/08	論文	Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits IPSJ Transactions on System LSI Design Methodology 6 (August issue),127-134頁 (共著)
2013	論文	A Don't Care Identification Method for Test Compaction PROCEEDINGS OF THE 2013 IEEE 16TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS),215-218頁
2013	論文	A Smart Trojan Circuit and Smart Attack Method in AES Encryption Circuits PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS),278-283頁
2013	論文	Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits IPSJ Transactions on System LSI Design Methodology 6 (August issue),127-134頁
2013	論文	スキャンベース攻撃への対策日本信頼性学会誌 35 (8),496
2013	論文	セキュリティLSIに対するタンパリングの手法日本信頼性学会誌 35 (8),492
2013	論文	設計自動化技術日本信頼性学会誌 25 (8),430
2012/02	論文	An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits IPSJ Transactions on System LSI Design Methodology 5 (February issue),63-70頁 (共著)
2012	論文	An exact estimation algorithm of error propagation probability for sequential circuits IPSJ Transactions on System LSI Design Methodology 5 (February issue),63-70頁
2012	論文	An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Information and Media Technologies 7 (2),593-600頁
2012	論文	Methodology for Early Estimation of Hierarchical Routing Resources in 3D FPGAs 2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC),213-218頁
2012	論文	Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS 2012 IEEE 18TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS),138-141頁
2011	論文	A Soft Error Tolerance Estimation Method for Sequential Circuits 2011 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT),268-276頁
2011	論文	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. 17th IEEE International On-Line Testing Symposium (IOLTS 2011)(IOLTS),151-156頁
2010/12	論文	キャプチャ時消費電力指向テスト生成における検出疑似外部出力決定法—A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation—システムLSI設計技術(SLDM) Vol.2010-SLDM-147 情報処理学会研究報告 2010年度 (4),6p
2010/09	論文	ソフトエラーに起因するパルスのラッチ確率のモデル化—Modeling of latching probability of soft-error-induced pulse—VLSI設計技術電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 110 (210),83-88頁
2010/09	論文	ソフトエラー耐性と面積オーバーヘッドとのトレードオフを考慮したTMRベースのエラー訂正手法 DAシンポジウム2010 : システムLSI設計技術とDA 2010 (7),245-250頁
2010/09	論文	デバイスシミュレータを用いた論理回路のソフトエラー解析 DAシンポジウム2010 : システムLSI設計技術とDA 2010 (7),251-256頁
2010/09	論文	順序回路のソフトエラー耐性評価手法の高速化 DAシンポジウム2010 2010 (7),239-244頁
2010/06	論文	TMR based Error Correction Method Considering Trade-off between Area and Soft-Error Tolerance Internathonal Workshop on Logic and Synthesis 2010 1,69-75頁
2010/06	論文	有限状態機械の分割に基づく定常状態確率の近似計算手法—An Approximate Method for Steady State Probability Calculation based on FSM Splitting—システムLSI設計技術(SLDM) Vol.2010-SLDM-145 情報処理学会研究報告 2010年度 (1),6p
2010/06	論文	順序回路のソフトエラー耐性評価における高精度な近似評価手法—Highly Accurate Approximate Methods for Soft Error Tolerance Estimation for Sequential Circuits—システムLSI設計技術(SLDM) Vol.2010-SLDM-145 情報処理学会研究報告 2010年度 (1),6p
2010	論文	Evaluation of Transition Untestable Faults Using a Multi-Cycle Capture Test Generation Method PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS,273-276頁
2009/08	論文	マルコフモデルを用いた順序回路のソフトエラー耐性評価手法 DA Symposium 2009,121-126頁
2009/03/04	論文	AI-1-6 ディペンダブルVLSI設計技術への挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画) 電子情報通信学会総合大会講演論文集 2009,"SS-41"-"SS-42"頁
2008/07/17	論文	暗号LSI におけるテスタビリティとセキュリティに関する一考察 FTC研究会 59
2008/02/08	論文	スキャンパス攻撃を考慮した暗号LSIのテスタビリティ評価—An evaluation of encryption LSI testability against scan based attack 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 107 (482),57-62頁
2006	論文	Development of practical ATPG tool with flexible interface PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM,129-129頁
2004	論文	SemanticObjects and Biomedical Informatics. 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004)(BIBE),497-502頁
2003	論文	ATPG パターン数削減指向テストポイント挿入方法電子情報通信学会論文誌 J86-D-I (12),884-896頁
2002	論文	A Test Point Insertion Method to Reduce the Number of Test Patterns. 11th Asian Test Symposium (ATS 2002),298-304頁
2001/11	論文	Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time IEICE Transaction on Fundamentals of Electronics, E84-A (11),2722-2730 (共著)
2001/11	論文	Novel DFT strategies using full/partial scan designs and test point insertion to reduce test application time IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A (11),2722-2730頁
2001/04	論文	ＲＴレベルパーシャルスキャン設計システム：ＲＥＰＳ情報処理学会論文誌 42 (4),1054-1061 (共著)
2001	論文	Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001(ASP-DAC),485-491頁
2001	論文	ＲＴレベルパーシャルスキャン設計システム：ＲＥＰＳ情報処理学会論文誌 42 (4),1054-1061頁
2000/04	論文	時間展開モデルを用いた無閉路順序回路の動的テスト系列圧縮方法の解析情報処理学会論文誌 41 (4),952-961 (共著)
2000	論文	時間展開モデルを用いた無閉路順序回路の動的テスト系列圧縮方法の解析情報処理学会論文誌 41 (4),952-961頁